This present invention relates to a fabricating method of semiconductor devices, and more particularly relates to trench isolation technology.
As the shift to high density and miniaturized semiconductor devices has progressed, there has been a growing necessity for secure isolation between counterpart devices such as transistors. In recent years, the trench isolation technique has been adopted to conduct isolation between counterpart devices. When utilizing the trench isolation technique, it has been usual to manufacture the semiconductor device according to the procedure shown in the sectional process diagram of FIGS. 5A to 5F.
First, as shown in FIG. 5A, a silicon substrate 51 which has undergone ion injection for purposes of well formation and a threshold voltage control is prepared, and then sequentially a gate oxide film 52 and a polysilicon film 53 are deposited on the surface of this silicon substrate 51. Subsequently, as shown in FIG. 5B, an element isolation trench 54 is formed in the interior of the silicon substrate 51 by dry etching after masking of the gate oxide film 52 and the polysilicon film 53 which have undergone patterning. Next, as shown in FIG. 5C, a silicon oxide film 55 is deposited as an insulating film having a conformable deposition shape by means of CVD utilizing silane type (SiH4) gas.
Next, when the surface is flattened by utilizing the chemical machinery polishing method (CMP method) or etch back method which uses the polysilicon film 53 as a stopper, the silicon oxide film 55 becomes embedded in the interior of the element isolation trench 54 which is formed in the silicon substrate 51, as shown in FIG. 5D. Furthermore, after a tungsten silicide film 56 is deposited as shown in FIG. 5E, the gate oxide film 52, polysilicon film 53 and tungsten silicide film 56 are subjected to patterning by dry etching, whereupon a transistor is completed with the required configuration and furnished with a gate electrode as shown in FIG. 5F.
When the semiconductor device is manufactured utilizing the trench isolation technique, the edge shape of the element isolation trench 54 exercises a major influence on the properties of the device. As shown in FIG. 5D, in the case where the surface of the silicon oxide film 55 embedded inside the element isolation trench 54 is etched lower than the surface of the silicon substrate 51, not only does there occur a hump phenomenon and a reverse narrow channel effect in the sub-threshold properties, but there also occurs an insufficiency in focal depth at the time of photolithography. In the flattening step when utilizing the trench isolation technique, it is necessary to perform a flattening treatment with superior in-plane uniformity and without pattern dependency. Consequently, it is necessary to make the film thickness of the silicon oxide film 55 during embedding as thin as possible, and to make the surface irregularities prior to flattening as small as possible.
However, as high density and miniaturization progress, it is necessary to form ever deeper element isolation trenches 54 between the device counterparts. Considering that it is necessary to deposit a silicon oxide film 55 of thick film thickness in order to bury a deep element isolation trench 54, one is compelled, as shown in FIG. 5C, to use a silicon oxide film 55 of thick film thickness possessing a conformable deposition shape. It is difficult to make the surface irregularities small prior to flattening. In particular, when the isolation trench 54 has a width more than twice the film thickness of the silicon oxide film 55, it is impossible to prevent the surface of the silicon oxide film 55, which is embedded in the isolation trench 54, from being etched lower than the surface of the silicon substrate. Furthermore, when the silicon oxide film 55 of thick film thickness is deposited, there is a reduction in the in-plane uniformity of the film thickness itself possessed by the silicon oxide film 55, and there is a problem that it is difficult to obtain superior in-plane uniformity after flattening.